GATE PH 2022 • Q59
NAT • 2 Marks
Section 8: Electronics
Digital Electronics
Subtopic: Boolean Algebra, De Morgan's Laws & Karnaugh Maps
Question Statement:
The minimum number of two-input NAND gates required to implement the
following Boolean expression is ________________
Y = [AB(C + BD) + A̅B]C
Official Answer Key:
3 to 3
Step-by-Step Solution & Explanation
### **Official Solution & Step-by-Step Derivation (GATE PH 2022 Q.59)**
**1. Digital Logic Boolean Simplification**:
- Given Boolean function:
$Y = \left[ A\bar{B}(C + BD) + \bar{A}\bar{B} \right] C$
**2. Detailed Step-by-Step Algebraic Reduction**:
- Step 1: Expand the term $A\bar{B}(C + BD)$:
$A\bar{B}(C + BD) = A\bar{B}C + A\bar{B}BD$
Since $\bar{B}B = 0$ by Boolean complementarity:
$A\bar{B}BD = 0 \implies A\bar{B}(C + BD) = A\bar{B}C$
- Step 2: Substitute back into the expression:
$Y = \left[ A\bar{B}C + \bar{A}\bar{B} \right] C = A\bar{B}C \cdot C + \bar{A}\bar{B}C$
Using $C \cdot C = C$:
$Y = A\bar{B}C + \bar{A}\bar{B}C = (A + \bar{A}) \bar{B}C$
Since $A + \bar{A} = 1$:
$Y = \bar{B}C$
- Step 3: Implement $Y = \bar{B}C$ using minimum 2-input NAND gates:
- Gate 1: Generate $\bar{B} = \overline{B \cdot B}$ (1 NAND gate).
- Gate 2: Generate $\overline{\bar{B} \cdot C}$ (1 NAND gate).
- Gate 3: Invert Gate 2 output: $\overline{\overline{\bar{B} \cdot C}} = \bar{B}C$ (1 NAND gate).
- Total minimum 2-input NAND gates required $= 3$.
**3. Official Verification**:
The verified official IIT Master Answer range is **3 to 3**.
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