QB_PH_SEC8_019: Semiconductor Devices & Diodes

In an enhancement-mode n-channel MOSFET (NMOS), conducting inversion layer channel formation between source and drain requires a gate-to-source voltage $V_{\text{GS}}$ that is

Correct Answer

### Step-by-Step Derivation & Verification: 1. **Enhancement Device Physics**: Built on a p-type silicon substrate with two heavily doped $n^+$ regions (source and drain). 2. **Equilibrium State ($V_{\text{GS}} = 0$)**: Two back-to-back $p-n$ junctions isolate drain from source; zero current flows (normally-OFF). 3. **Channel Inversion**: When a positive gate voltage $V_{\text{GS}} > 0$ is applied, holes are repelled from the interface. When $V_{\text{GS}}$ exceeds the positive threshold voltage $V_{\text{th}}$, the surface potential reaches $2\phi_F$ (strong inversion), accumulating an electron inversion layer bridging source and drain. 4. **Conclusion**: Requires $V_{\text{GS}} > V_{\text{th}} > 0$. Option (A) is correct.