Question Bank MCQ • 2 Marks Section 8: Electronics Digital Electronics

QB_PH_SEC8_017: Digital Electronics

Question Statement

In a J-K flip-flop, what is the next state $Q_{n+1}$ when both inputs are held at logic HIGH ($J = 1, K = 1$) upon the arrival of a clock trigger pulse?
(A) Toggle state ($Q_{n+1} = \bar{Q}_n$)
(B) Reset state ($Q_{n+1} = 0$)
(C) Set state ($Q_{n+1} = 1$)
(D) No change ($Q_{n+1} = Q_n$)
Correct Answer
A
Verified Key

Step-by-Step KaTeX Derivation & Detailed Explanation

### Step-by-Step Derivation & Verification: 1. **J-K Flip-Flop Characteristic Truth Table**: - $J = 0, K = 0 \implies Q_{n+1} = Q_n$ (Memory / Hold) - $J = 0, K = 1 \implies Q_{n+1} = 0$ (Reset) - $J = 1, K = 0 \implies Q_{n+1} = 1$ (Set) - $J = 1, K = 1 \implies Q_{n+1} = \bar{Q}_n$ (Toggle) 2. **Algebraic Characteristic Form**: $Q_{n+1} = J\bar{Q}_n + \bar{K}Q_n$ For $J = 1, K = 1$: $Q_{n+1} = (1)\bar{Q}_n + (0)Q_n = \bar{Q}_n$ 3. **Conclusion**: Toggle operation. Option (A) is correct.
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